产品资讯 - GPBA02B

General Description

GPBA02B, a newly invented I/O extender for micro-controller extending I/O pads application, equips with a standard SPI (Mode 0) communication-processing block and 24 I/O ports. With high-speed bit operation of AND/OR/XOR for each bit in internal configuration registers, I/Os’ status can be modified within fewer host CPU cycles.  These I/Os are provided with strong driving capability to drive LED directly.  GPBA02B furnishes 16 PWMIO channels, and there are two sets of constant-current sink function dedicated for these PWMIO channels to use.  GPBA02B is fully compatible with GPBA02A.

Features

• Operating Voltage
  • Chip operating voltage (VDD): 2.0V – 5.5V
  • I/O operating voltage (VDDIO): 2.0V – 5.5V
• Standard SPI（Mode 0）Interface
  • Four pins for SPI communication
  • Chip Selecting Signal (CSB) as transmitting enable signal
  • Serial clock SCK (max 8MHz) as data synchronization signal for transmitting and receiving data
  • To receive command and data from host via MOSI pin
  • To transmit data to host via MISO pin
• 24 I/Os
• 24 bi-directional I/O lines
• Selecting pull high/low resistors or buffer/open-drain outputs via corresponding registers.
• To execute high-speed AND/OR/XOR function of each bit in I/O configuration registers through writing to the corresponding registers.
• • 16 PWMIO Output Channels
    • Sixteen 256-step channels, PA[7:0] and PC[7:0]
  • Two sets of constant current sink functions for 16 PWMIO channels
    • Two sets of four-level constant current sink, PA[7:0] and PC[7:0]
  • Four CMOS Inverters
    • PB[0] input with PB[1] CMOS inverting output
    • PB[3] input with PB[2] CMOS inverting output
    • PB[4] input with PB[5] CMOS inverting output
    • PB[7] input with PB[6] CMOS inverting output
  • Four Interrupt Sources
    • Four interrupt sources (PA[3:0])
    • One output interrupt flag (PA[4])
  • Reset Management
    • Power on reset
    • Software control reset