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Products - GPA7740A


Shipment formCPUFPUCacheInternal RAMDRAM Type & DensityNAND & ECCSDC SD3.0USB 2.0 Host/DeviceLCDHDMIGPUGraphic EngineSound EngineCamera InputISP(CDSP)GPDLAUART/IrDASPII2CI2SDACADCAESSecurityTrust ZoneRTCPWM I/Omaximum GPIO numberMultimedia CodecMP3Ethernet MAC
LQFP128ARM Cortex-A7 660MHz2KB/32KB L2: 128KBNEON, FPUL1: 32KB/32KB L2: 128KBmax 470KBpenGL ES2.0, OpenVG 1.1DDR2 64MB12bit ECCx2 •2/2MIPI/TFT/ CSTN/STN0P w/ HDCP1080P3D GPUPPU16Ch2XMIPI/CCIR656/CCIR60113M RAW64MACx3x2x36xI 6xO16bitx2MIC/Line-in256bitsSHA-512, RSA-2048, TRNG, OTP• (indep. power)x872MJPEG, H.264 1080P60 HP

General Description

GPA7740A, a highly integrated SoC (System-On a Chip) by Generalplus, is a high cost-performance ratio solution for multi-media, video streaming and AI applications. It is developed with a high performance and power efficient 32-bit single-core ARM Cortex-A7. GPA7740A can be operated at up to CPU/system 666/222MHz with significant enhancements in ISP processing, 2D/3D Graphics accelerating, video CODEC processing, audio process, deep learning accelerating and a rich set of peripherals.


  • 32-bit Single-Core Arm Cortex-A7
    • L1 32-Kbyte I Cache / 32-Kbyte D Cache
    • 128-Kbyte Unified Level 2 Cache, Embedded JTAG
    • With NEON and FPU
    • ICE with SWD/JTAG Interface
    • Working frequency up to 666MHz.
  • Up to 470KB SRAM (Dedicated 128KB SRAM) for local data buffer
  • DDR2 SDRAM controller with 16-bit data bus supports up to 1066Mbps (DDR2 clock 533MHz).
  • SPI FLASH controller allows CPU directly running program on it, and supports 1-bit/2-bit/4-bit IO mode.
  • 3D GPU supports OpenGL ES2.0, OpenVG 1.1
    • Up to 22 Mtriangle/s, 112 Mpixel/s
  • Picture Process Unit (PPU)
    • Four Text layers + 1024 internal Sprites + 4096 extended Sprites
    • Virtual 3D effect for text and sprite.
    • QVGA/VGA/D1 and arbitrary size up to 2032x2032 output.
    • Line-Based or Frame-Based Operation
    • 1920x1080 LCD Resolution Output
    • Texture mapping with anti-aliasing and bilinear interpolation.
  • Sound Process Unit (SPU)
    • 16 Hardware PCM/ADPCM Channels
    • Built-in Dynamic Volume Compressor
    • MP3/WMA Decoder
    • ISO/IEC 10918-1 Baseline JPEG
    • High-speed decoding and encoding with resolution up to 64MPixel.
    • Hardware Motion JPEG decoding and encoding (up to 1080p 70fps at Q70) for real-time video record and playback application.
  • 264 CODEC supports up to 2560x1440 30fps.
    • FBC(Frame buffer compression) is supported for reference frame accessing.
  • Video-in & CMOS sensor interface and CCIR601/CCIR656 CSI standard are supported.
  • One 2-lane MIPI CSI input supported with data rate up to 1.3Gbps.
  • One of 4/2-lane MIPI CSI input supported with data rate up to 1.3Gbps.
  • Bnning mode engine A for 2-lane MIPI CSI input
    • Support divide 2 & 4 binning
    • Support skip and average mode
    • Support RAW8 and RAW10
    • Support input image crop
    • Support bypass mode
  • Bnning mode engine B for 4-lane MIPI CSI input
    • Support divide 2 & 4 binning
    • Support skip and average mode
    • Support RAW8 and RAW10
    • Support input image crop
    • Support bypass mode
    • Support 4 virtual channel input from 4-lane MIPI CSI input
  • GPDLAv2 is a deep learning accelerator which supports various deep neural network models. Applications such as object classifications, object detection and face detection are all possible, and will enrich user experience.
  • NAND FLASH controller with ECC and 4/8/12-bit BCH.
  • Eight-Channel DMA Controller
  • Security H/W Accelerator:
    • AES supports key length 128-bit/192-bit and 256-bit.
    • HASH supports SHA2-256 / SHA2-512 / SHA3-224 / SHA3-256 / SHA3-384 and SHA3-512 for AES GCM mode.
    • RSA supports data length 256/512/1024 and 2048-bit.
    • True Random Number Generator
  • Y-only rotating engine supports rotate in any angle.
  • Rotating engine supports 90/180/270/360/Mirror/Flip function.
  • Line-based rotating engine can rotate a DRAM image buffer by the multiples of 90 degrees. With TFT controller, the rotated data will be sent to TFT controller directly, and there won’t be any extra bandwidth consumption.
  • Two Sets of TFT-LCD Controller
    • UPS051 (Serial RGB)
    • UPS052 (Serial RGB dummy)
    • Parallel RGB (6-6-6, 5-6-5, 8-8-8)
    • I80 (8-bit/16-bit/18-bit System Bus) I/F Type
    • CCIR601/CCIR656
    • Built-in Timing Controller for TFT-LCD drivers.
    • Scaling engine inside with programmable up-scaling and down-scaling factor.
    • Gamma Table Adjustment (TFT1 Only)
  • Two Sets of TFT SPI interface controller
    • Supports programmable resolutions up to 320x320
    • The TFT clock can be a divisor of system clock (/2, ~ /64)
    • Support both 3-wire mode and 4-wire mode
  • Up to two-lane MIPI DSI interface which supports panel resolution up to 720x1920.
  • HDMI with HDCP resolution up to 1080p.
  • Two sets of Pscaler support transform and zoom-in/out image data to the format supported by JPEG/ISP/PPU MB2SCAN/DRAM.
  • One Y-only Pscaler for gray level output.
  • Embedded ISP (Image Processing Unit) supports raw data sensor up to 8M pixels.
    • Histogram statistics for auto brightness and contrast.
    • Programmable RGB Gamma Correction
    • Color conversion matrix for various post-image processing.
    • 2nd Generation Lens Uniform Correction
    • WDR
    • Sharpen
    • Bad-Pixel Cancelation
    • AE/AWE
    • 2D NLM De-noise
    • 3DNR
    • Binning Mode
  • Image Processing Unit
    • Maximum width more than 2048 pixels.
    • Address-remap supports direct addressing and coordinates addressing.
    • Color-remap only supports ARGB1555 and RGB565.
    • Sixteen OP modes are supported.
    • Alpha transform is supported.
  • FFT Accelerator
    • Support FFT32, FFT64, FFT128, FFT256, FFT512, FFT1024, and FFT2048.
    • Internal 24-bit accuracy for FFT calculation.
  • Two sets of Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB OHCI/EHCE host controller with built-in transceiver.
  • Watchdog Timer
  • Eight 32-bit timers/counters with PWM output capability.
  • Eight-Channel Quadrature Decoder
  • SD 2.0/MMC Interface
  • SD 3.0 Interface
  • Two sets of SPI (master/slave) interface with data rate up to 24Mbps.
  • Three sets of UART (asynchronous serial I/O) or IrDA interface with baud rate up to 1.8432Mbps and 115.2Kbps. Smart card interface (ISO7816) is also supported.
  • Four sets of I2S input with 24-bit resolution and up to 192KHz sample rate.
  • Four sets of I2S output with 24-bit resolution and up to 192KHz sample rate.
  • Three sets of I2C
  • PDM to PCM converter which supports MEMS microphones with PDM interface.
  • Embedded Ethernet MAC Hardware
  • One set of hardware 3x3 box filter engine.
    • Resolution support up to 640x480
    • Y-only 3x3 filter, filer coefficients are programmable
  • LBP (Local Binary Patterns) and the maximum resolution is 640x480 pixels.
  • 86 general programmable I/O ports (GPIO) with pull-high/low control.
  • Power management integrates SD3.0 LDO, Sensor LDO, PLLs LDO. It also includes 4*Power-on key control and RTC wakeup control.
    • RTC has an independent power pad, and if the pad is always powered on, RTC can perform functions including issuing alarm and waking up the whole system.
    • Built-in 32KHz internal oscillator for no 32KHz crystal application, or quick startup of the system for the first time when RTC is powered on.
    • 3V to 2.8V regulator for sensor’s power.
    • Dedicated 3.3V to 1.8V LDO for SD 3.0 I/O.
    • Dedicated 3.3V to 2.8V LDO for PLLs.
    • Power on Reset and Low Voltage Reset
    • OVP11 (Over Voltage Protection) Detect
    • When the power of some IOs is kept in core power off mode, and these IOs and USB can wakeup the whole chip.
    • Power-down mode with low standby current, typically around 6uA.
  • Programmable system PLL frequency, from 216MHz to 1188MH, for CPU, and with a divider, the frequency can also be provided to system clock.
  • Programmable external PLL frequency from 72MHz to 639MHz for HDMI/TFT/GPDLA/GPU etc.
  • Audio PLL frequency can output 73.728MHz for 48KHz sampling-rate, and output 67.737MHz for 44.1KHz sampling-rate.
  • 16-bit stereo DAC (2-channel) for audio playback.
  • 12-bit SAR ADC with 5 line-in channels and 687.5Ksps.
  • Temperature sensor
  • 16-bit SDM ADC with MIC for audio recording.
  • MIC with Digital AGC (Auto Gain Control)
  • Audio compressor for audio dynamic range adjustment. Both microphone input and DAC output are supported.
  • LQFP128 with e-Pad Package
  • Operation voltage: I/O 3.3V, Core 1.1V, DDR2 1.8V.
  • Operation temperature: -20~85C.

Data Sheet

GPA7740AV13_ds.pdf   Copy Link.
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