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GPA7775A

Description
Document
Tools
Sample Code
Video

Shipment form	CPU	FPU	Cache	Internal RAM	DRAM Type & Density	NAND & ECC	SDC SD3.0	USB 2.0 Host/Device	LCD	HDMI	GPU	Graphic Engine	Sound Engine	Camera Input	ISP(CDSP)	GPDLA	UART/IrDA	SPI	I2C	I2S	DAC	ADC	AES	Security	Trust Zone	RTC	PWM I/O	maximum GPIO number	Multimedia Codec	MP3	Ethernet MAC
LQFP128	ARM Cortex-A7 660MHz2KB/32KB L2: 128KB	NEON, FPU	L1: 32KB/32KB L2: 128KB	max 470KBpenGL ES2.0, OpenVG 1.1	DDR2 64MB	12bit ECC	x2 •	2/2	MIPI/TFT/ CSTN/STN0P w/ HDCP	1080P	3D GPU	PPU	16Ch	2XMIPI/CCIR656/CCIR601	13M RAW	64MAC	x3	x2	x3	6xI 6xO	16bitx2	MIC/Line-in	256bits	SHA-512, RSA-2048, TRNG, OTP	•	• (indep. power)	x8	72	MJPEG, H.264 1080P60 HP	•	•

General Description

GPA7775A, a highly integrated SoC (System-On a Chip) by Generalplus, is a high cost-performance ratio solution for multi-media, video streaming and AI applications. It is developed with a high performance and power efficient 32-bit single-core ARM Cortex-A7. GPA7775A can be operated at up to CPU/system 666/222MHz with significant enhancements in ISP processing, 2D/3D Graphics accelerating, video CODEC processing, audio process, deep learning accelerating and a rich set of peripherals.

Features

32-bit single-core Arm Cortex-A7
- L1 32-Kbyte I cache / 32-Kbyte D cache
- 128-Kbyte unified level 2 cache, embedded JTAG
- With NEON and FPU
- ICE with SWD/JTAG interface
- Working frequency up to 666MHz.
Up to 470KB SRAM (Dedicated 128KB SRAM) for local data buffer.
LPDDR2 SDRAM controller with 16-bit data bus supports up to 1068Mbps (LPDDR2 clock 534MHz).
SPI FLASH controller allows CPU directly running program on it, and supports 1-bit/2-bit/4-bit IO mode.
3D GPU, API supports OpenGL ES2.0, OpenVG 1.1
- Up to 22 Mtriangle/s, 112 Mpixel/s
Picture Process Unit (PPU)
- Four Text layers + 1024 internal Sprites + 4096 extended Sprites
- Virtual 3D effect for text and sprite.
- QVGA/VGA/D1 and arbitrary size up to 2032x2032 output.
- Line-Based or Frame-Based Operation
- 1920x1080 LCD Resolution Output
- Texture mapping with anti-aliasing and bilinear interpolation.
Sound Process Unit (SPU)
- 16 Hardware PCM/ADPCM Channels
- Built-in Dynamic Volume Compressor
- MP3/WMA Decoder
Two sets of JPEG CODEC.
- ISO/IEC 10918-1 Baseline JPEG
- High-speed decoding and encoding with resolution up to 64MPixel.
- Hardware Motion JPEG decoding and encoding (up to 1080p 70fps at Q70) for real-time video record and playback application.
264 CODEC supports resolution up to 2560x1440 30fps or dual 1080P 30fps.
- FBC(Frame buffer compression) is supported for reference frame accessing.
Video-in & CMOS sensor interface and CCIR601/CCIR656 CSI standard are supported.
A 2-lane MIPI CSI input is supported with data rate up to 800Mbps/lane.
A 4/2-lane MIPI CSI input is supported with data rate up to 800Mbps/lane.
Binning mode engine A for 2-lane MIPI CSI input supports:
- Divide 2 & 4 binning
- Skip and average mode
- RAW8 and RAW10
- Input image crop
- Bypass mode
Binning mode engine B for 4-lane MIPI CSI input supports:
- Divide 2 & 4 binning
- Skip and average mode
- RAW8 and RAW10
- Input image crop
- Bypass mode
- Up to 4 virtual channel input from 4-lane MIPI CSI input.
GPDLAv2 is a deep learning accelerator which supports various deep neural network models. Applications such as object classifications, object detection and face detection are all possible, and will enrich user experience.
NAND FLASH controller with ECC and 4/8/12-bit BCH.
Eight-Channel DMA Controller
Security H/W Accelerator:
- AES supports key length 128-bit/192-bit and 256-bit.
- HASH supports SHA2-256 / SHA2-512 / SHA3-224 / SHA3-256 / SHA3-384 and SHA3-512 for AES GCM mode.
- RSA supports data length 256/512/1024 and 2048-bit.
- 4Kb OTP for Security
- Supports ARM standard Trust Zone.
- True Random Number Generator
Y-only rotating engine supports rotate at any angle
Rotating engine supports 90/180/270/360/Mirror/Flip function.
Line-based rotating engine can rotate a DRAM image buffer by the multiple of 90 degrees. With TFT controller, the rotated data will be sent to TFT controller directly, and there won’t be any extra bandwidth consumption.
Two Sets of TFT-LCD Controller
- UPS051 (Serial RGB)
- UPS052 (Serial RGB dummy)
- Parallel RGB (6-6-6, 5-6-5, 8-8-8)
- I80 (8-bit/16-bit/18-bit System Bus) I/F Type
- CCIR601/CCIR656
- Built-in Timing Controller for TFT-LCD drivers.
- Scaling engine inside with programmable up-scaling and down-scaling factor.
- Gamma Table Adjustment (TFT1 Only)
Two Sets of TFT SPI interface controller
- Supports programmable resolutions up to 320x320
- The TFT clock can be a divisor of system clock (/2, ~ /64)
- Support both 3-wire mode and 4-wire mode
Up to two-lane MIPI DSI interface with panel resolution up to 720x1920 is supported.
Two sets of Pscaler support transform and zoom-in/out image data to the format supported by JPEG/CDSP/PPU MB2SCAN/DRAM.
HDMI v1.4 with HDCP resolution up to 1080p.
One Y-only Pscaler for gray level output.
Embedded ISP (Image Processing Unit) supports raw data sensor up to 13M pixels.
- Histogram statistics for auto brightness and contrast.
- Programmable RGB Gamma Correction
- Color conversion matrix for various post-image processing.
- 2^nd Generation Lens Uniform Correction
- WDR
- Sharpen
- Bad-Pixel Cancelation
- AE/AWE
- 2D NLM De-noise
- 3DNR
- Binning Mode
- Auto Focus
- In auto mode, sensor input will go through ISP and be output to USB directly. Latency < One Frame.
Image Processing Unit
- Maximum width more than 2048 pixels.
- Address-remap supports direct addressing and coordinates addressing.
- Color-remap only supports ARGB1555 and RGB565.
- Sixteen OP modes are supported.
- Alpha transform is supported.
FFT Accelerator
- Supports FFT32, FFT64, FFT128, FFT256, FFT512, FFT1024, and FFT2048.
- Internal 24-bit accuracy for FFT calculation.
Two sets of Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB OHCI/EHCE host controller with built-in transceiver, up to 24MB/sec@UVC.
Watchdog Timer
Eight 32-bit timers/counters with PWM output capability.
Eight-Channel Quadrature Decoder
SD 2.0/MMC Interface
SD 3.0 Interface, up to 100MHz.
Two sets of SPI (master/slave) interface with data rate up to 24Mbps.
Three sets of UART (asynchronous serial I/O) or IrDA interface with baud rate up to 1.8432Mbps and 115.2Kbps. Smart card interface (ISO7816) is also supported.
Three sets of I2C controller
Four sets of I2S input with 24-bit resolution and up to 192KHz sample rate.
Four sets of I2S output with 24-bit resolution and up to 192KHz sample rate.
PDM to PCM converter which supports MEMS microphones with PDM interface.
Embedded Ethernet MAC Hardware
Hardware 3x3 Box Filter Engine
- Resolution support up to 640x480
- Y-only 3x3 filter, filer coefficients are programmable
LBP (Local Binary Patterns) accelerator supports up to 640x480 resolution.
86 general programmable I/O ports (GPIO) with pull-high/low control.
Power management integrates SD3.0 LDO, Sensor LDO, PLLs LDO. It also includes 4*Power on key control and RTC wakeup control.
- RTC has an independent power pad, and if the pad is always powered on, RTC can perform functions including issuing alarms and waking up the whole system.
- Built-in 32KHz internal oscillator is for no 32KHz crystal application, or quick startup of the system for the first time when RTC is powered on.
- 3V to 2.8V regulator for sensor’s power.
- Dedicated 3.3V to 1.8V LDO for SD 3.0 I/O.
- Dedicated 3.3V to 2.8V LDO for PLLs.
- Power on Reset and Low Voltage Reset
- OVP11 (Over Voltage Protection) Detect
- When the power of some IOs is kept in core power off mode, these IOs and USB can wakeup the whole chip.
- Power-down mode with low standby current, typically around 6uA.
Programmable system PLL frequency, from 216MHz to 1188MH, for CPU, and with a divider, the frequency can also be provided to the system clock.
Programmable external PLL frequency from 72MHz to 639MHz for HDMI/TFT/GPDLA/GPU etc.
Audio PLL frequency can output 73.728MHz for 48KHz sampling-rate, and output 67.737MHz for 44.1KHz sampling-rate
16-bit stereo DAC (2-channel) for audio playback.
16-bit ADC with MIC for audio recording.
12-bit SAR ADC with 5 line-in channels and 75Ksps
Temperature sensor.
MIC with Digital AGC (Auto Gain Control)
Audio compressor for audio dynamic range adjustment. Both microphone input and DAC output are supported.
Boot mode is selectable: the system code can be booted from SPI Flash, SD card, NAND Flash, or USB.
LFBGA 148L Package
Operating voltage: I/O 3.3V, Core 1.1V, LPDDR2 1.25V.
Operating temperature: -20~85C.