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Products - GPCV1167B


Major Camera ResolutionSIP DRAM DensityLCD I/FPackageWi-Fi

General Description

GPCV1167B, a highly integrated SoC (System-On a Chip) by Generalplus, is a high cost-performance ratio solution for multi-media and video streaming applications.  It is developed with a high performance and power efficient ARM’s ARM926EJ-S core operating at up to CPU/system 513/171MHz with significant enhancements in image, video processing, and power savings.  Other features include DDR memory, 1080p30 H.264/JPEG CODEC engine, TFT-LCD interface, CMOS sensor interface, MIPI CSI interface, scaling engine, Picture Process Unit (PPU), 16-channel Sound Process Unit (SPU), USB 2.0 OHCI/EHCI, USB 2.0 HS device, etc. GPCV1167B processor is designed to connect with various types of memory card interfaces such as SD and MMC.  For more information about its features, please refer to the following section.


  • ARM926EJ-S CPU with both 16K-byte I/D-cache, 64KB TCM embedded JTAG ICE, and working frequency up to 513MHz.
  • Up to 220KB SRAM for local data buffer
  • Embedded 128Mb DDR SDRAM
  • SPI FLASH controller, allowing CPU directly runs program on it. Supports 1-bit/2-bit IO mode
  • Picture Process Unit (PPU)
    • Four Text layers + 1024 internal Sprites + 4096 extended Sprites
    • Virtual 3D effect for text and sprite
    • QVGA/VGA/D1 and arbitrary size up to 2032x2032 output
    • Line-based or frame-based operation
    • Texture mapping with anti-aliasing and bilinear interpolation
  • Sound Process Unit (SPU)
    • 16 hardware PCM/ADPCM channels
    • Dynamic volume compressor
    • MP3/WMA decoder
    • ISO/IEC 10918-1 baseline JPEG
    • High-speed decoding and encoding with resolution up to 64M pixels
    • Hardware Motion JPEG decoding and encoding (up to 1080p@30fps) for real-time video record and playback application
  • 264 CODEC
    • 264 high profile CODEC
    • Up-to 720p60 or 1080p30 for real-time video record and playback application
  • Video-in & CMOS sensor interface and CCIR601/CCIR656 CSI standard supported
  • One set of two-lane and one set of one-lane MIPI CSI input supported
  • Two Face Detection Engines for interactive application
  • Eight-channel DMA controller with AES/DES/3DES function
  • Mono and 16 gray levels STN-LCD controller
  • Rotating engine supports 90/180/270/360/Mirror/Flip function
  • Y-only rotating engine supporting rotate at any angle
  • TFT-LCD controller
    • I80 (8-bit system bus) I/F type
    • CCIR601/CCIR656
    • Timing Controller for TFT-LCD drivers
    • Scaling engine inside with programmable up-scaling and down-scaling factor
    • Gamma Table Adjustment(TFT1 Only)
  • Two sets of PSCAL supporting transform and zoom-in/out image data to the format supported by JPEG/ CDSP/ PPU/ H264 MB2SCAN/ DRAM
  • One Y-only PSCAL for face-detection engine
  • Embedded ISP (Image Processing Unit), supporting raw data sensor up to 5M pixels
    • Histogram statistics for auto brightness and contrast
    • Programmable RGB gamma correction
    • Color conversion matrix for various post-image processing
    • Lens Uniform Correction
    • WDR
    • Sharpen
    • De-noise
    • Bad-pixel cancellation
    • AE/AWE
    • Binning Mode
  • Image Processing Unit
    • width more than 2048 pixels
    • Address-remap support direct addressing and Coordinates addressing
    • Color-remap only support ARGB155 and RGB565
    • Sixteen OP modes supported
    • Alpha transform supported
  • Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB OHCI/EHCE host controller with built-in transceiver
  • Watchdog timer
  • Real-time clock
  • Eight 32-bit timers/counters with PWM output capability
  • Eight-channel quadrature decoder
  • Two sets of SD 2.0/MMC interface
  • Two sets of SPI (master/slave) interface with data rate up to 24Mbps
  • Two UART/Tx and one UART/Rx (asynchronous serial I/O) or IrDA interface with baud rate up to 1.8432Mbps and 115.2Kbps; smart card interface (ISO7816) supported
  • Two sets of I2C controller
  • One hardware 3x3 box filter engine
  • One hardware SAD(Sum of Absolute Difference) engine
  • One up to 320x240 pixels LBP(Local Binary Patterns)
  • 37 general programmable I/O ports (GPIO) with pull-high/low control
  • Power management
  • 3V to 2.8V regulator for sensor’s power
  • 3V to 1.8V regulator for sensor’s power
  • 3V to 2.5V regulator for DDR memory
  • Dedicated 3.3V to 3.0V LDO for audio ADC
  • Dedicated 3.3V to 3.0V LDO for PLLs
  • Low voltage reset
  • RTC with independent power supply
  • Power-down mode with low standby current, typically less than 40uA
  • Programmable PLL frequency from 54MHz to 1026MHz
  • 16-bit DAC for audio playback
  • 16-bit ADC with MIC for audio recording
  • 12-bit SAR ADC with 1 line-in channels and 100Ksps
  • MIC with digital AGC (auto gain control)
  • QFN 64 package


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