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Products - GPM8F3132B


ROM TypeWorking Voltage (V)Speed (MHz)ROM (Byte)RAM (Byte)ADC (12bit)CORDICmotor BLDCmotor Sensor-lessmotor SINTMR/CNTCPU OSC. IntCPU OSC. X'TALOP/ComparatorMDULVRIO No.UART/SPI/12CPreDriver for SOCPKG
Flash2.4~5.54832K1K/2568-ch/2set-VVV5VV3/4 3/1VV43 251/1/1-LQFP48 SSOP28

General Description

The GPM8F3132B, a highly integrated microcontroller, features a pipelined 1T 8051-based CPU, 1K-byte XRAM, 256-byte IDM SRAM, and 32K-byte program FLASH memory into a single chip. It supports up to 43 programmable multi-functional I/Os, Timer0/1/A/B/C, UART0, SPI (master/slaver), I2C (master/slaver), three sets of OP, 48MHz PLL, 16-bit x 16-bit multiplier, 32-bit / 16-bit divider and two sets of 8-channle SAR ADC with 12-bit resolution for general-purpose application. It operates over a wide voltage range of 2.4V - 5.5V with variety of clock sources. It also provides one power saving mode in power management unit to manage power consumption more efficiently. Moreover, there is an on-chip debug circuit with two pins equipped to facilitate a full speed in-system debug while in application development phase.


  • CPU
    • High speed and high performance 1T 8051-based CPU
    • 100% software compatible with industry standard 8051
    • Pipeline RISC architecture enables to execute   instructions 10 times faster than standard 8051
    • Up to 48MHz clock operation
  • Memories
    • 1K bytes XRAM
    • 256 bytes internal Data Memory (IDM) SRAM
    • 32K bytes Flash with high endurance
  • Minimum 200,000 program/erase cycles
  • Minimum 20 years data retention
  • 1KB page size
  • Programming read only level for software security
  • Clock Management
    • Internal oscillator: 16MHz±2% @ 2.4V~5.5V
    • Internal oscillator with PLL : 48MHz
  • Power Management
    • One Sleep mode for power saving
  • Interrupt Management
    • 13 interrupt sources
    • Up to 6 external interrupt sources
  • Reset Management
    • Power On Reset (POR)
    • Low Voltage Reset (LVR)
    • Pad Reset (PAD_RST)
    • Watchdog Reset (WDT_RST)
    • Software Reset (S/W_RST)
    • Flash Access Error Reset (ADDR_ERR_RST)
  • Programmable Watchdog Timer
    • A time-base generator
    • An event timer
    • System supervisor
  • Three OPs
  • I/O Ports
    • Max. 43 multifunction bi-direction I/Os
    • Each incorporates with pull-up resistor, pull-down resistor, output high, output low , output driving capability and floating input, determined by user's settings at the corresponding registers
    • I/O ports with 12mA or 6mA current sink
    • I/O ports with 12mA or 6mA current drive
  • Two 16-bit Timers/Counters (Timer 0/1)
    • Timer mode with selectable clock source
    • Auto reload 8-bit timers
  • Three Powerful Timers: TimerA / TimerB / TimerC, with 16-bit Compare / Capture / PWM Unit
    • Timer mode with selectable clock source
    • Auto-reload 16-bit timers
    • Event capturing
    • Pulse width modulation and measurement
  • UART0
    • One synchronous mode
    • Three asynchronous modes
  • SPI (master / slaver mode)
    • Programmable phase and polarity of master clock
    • Programmable master SPI clock frequency
    • Max. SPI clock: 24MHz (Fpll /2) @48MHz
  • I2C (master / slaver mode)
    • Programmable master I2C clock frequency
    • Max I2C clock: 375KHz (Fpll /128) @48MHz
  • A/D Converter
    • Two 8-channel 12-bit resolution ADC
    • Control independent per set
  • Built-in Low Voltage Reset
    • Trigger level: 1.9V, 2.4V, 3.2V, 4.2V
  • Built-in Low Voltage Detect
    • Programmable level: 2.1V, 2.6V, 3.4V, 4.4V
  • MDU
    • Built-in 16-bit X 16-bit signed multiplier
    • Built-in 32-bit / 16-bit signed divider
  • On-chip Debug Unit
    • C compatible development tools

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