General Description
The GPL31B3, an 8-bit CMOS single chip microprocessor, contains RAM, ROM, I/Os, interrupt/wakeup controller, timer, 8-bit PWM audio output and automatic display controller/ driver for LCD. With a dual channel PWM driver, attractive sound effects can be generated easily. Built-in voltage doubler and voltage regulator provide robust and adjustable (16-level) LCD supply voltage to get the best display quality for specific panels. Furthermore, a software controllable standby mode is also implemented for power saving. The GPL31B3 is designed with state-of-the-art technology to fulfill the requirements of LCD applications especially for hand-held products.
Features
- Built-in 8-bit CPU
- 160 bytes SRAM
- 64K bytes ROM
- Max. CPU clock: 3.0MHz @ 2.4V – 5.5V
- Programmable CPU clock frequency, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of R-oscillator's clock frequency is available
- Provides 7 interrupt sources
- Built-in 8-bit 2-channel PWM outputs
- Built-in 32.768KHz Crystal / R-oscillator
- Crystal or R-oscillator (mask option)
- Crystal oscillator switches from strong to Weak mode automatically
- Internal time base generator
- Built-in System R-oscillator
- Only one resistor is needed
- Two 16 bits timer/counters
- Low Voltage Reset / Low Voltage Detect
- Provides 2.3V low voltage reset function
- 2.4V/2.6V low voltage detect (Mask option)
- Low power consumption
- Operating current: 1.0mA/1.0MHz @ 3.0V
- Very low standby current : ISTBY < 1.0μA @ 3.0V In standby mode: stop all oscillators
- Max. 12 general purpose I/O
- SEG[43:41] can be optioned to IOEF[7:5]
- 8 IO pins support Key wake-up mode
- LCD controller / driver
- 44 segments x 5 commons, max. 220 dots
- Programmable bias option (1/2,1/3 bias) and duty option (1/2,1/3,1/4,1/5 duty)
- Built-in voltage doubler and regulator to generate VLCD voltage for LCD driver(Built-in regulator can be disabled)
- Adjustable 16-level VLCD for various panels 1/3 bias: VLCD (3.0V - 6.0V) 1/2 bias: VLCD (2.0V - 4.0V)
- Built-in regulator can be disabled 1/3 bias: VLCD = VDD ;VDD2 =2/3 VDD ;VDD1 =1/3 VDD 1/2 bias: VLCD = VDD ;VDD1 =1/2 VDD