产品资讯 - GP328525C

General Description

GP328525C, a highly integrated SoC (System-On a Chip) by Generalplus, is a high cost-performance ratio solution for multi-media and video streaming applications.  It is developed with a high performance and power efficient ARM’s ARM926EJ-S core operating at up to CPU/system 513/171MHz with significant enhancements in image, video processing, and power savings.  Other features include DDR memory, GPDLA deep learning accelerator, Chroma key engine, JPEG CODEC engine, TFT-LCD interface, MIPI DSI interface, Display adjustment engine, CMOS sensor interface, MIPI CSI interface, scaling engine, Picture Process Unit (PPU), 16-channel Sound Process Unit (SPU), audio compressor, USB 2.0 OHCI/EHCI, USB 2.0 HS device, etc. GP328525C processor is designed to work with various types of memory card interfaces such as SD and MMC.  For more information about its features, please refer to the following section.

Features

• ARM926EJ-S CPU with both 16K-byte I/D-cache, embedded JTAG ICE, and working frequency up to 513MHz
• Up to 238KB SRAM for local data buffer
• Embedded 128Mb DDR SDRAM
• Embedded 2Gb SLC NAND Flash
• GPDLA is a deep learning accelerator which supports various deep neural network models; applications such as object classification, object detection and face detection are all possible and will enrich user experience.
• Chroma key engine with robust mechanism and low bandwidth requirements
• SPI FLASH controller, allowing CPU directly runs program on it. 1-bit/2-bit/4-bit IO mode supported
• Picture Process Unit. (PPU)
  • Four Text layers + 1024 internal Sprites + 4096 extended Sprites
  • Virtual 3D effect for text and sprite
  • QVGA/VGA/D1 and arbitrary size up to 2032x2032 output
  • Line-based or frame-based operation
  • 1024x768 LCD Resolution output
  • Texture mapping with anti-aliasing and bilinear interpolation
  • High precision sprite rotate effect supports up to 256-step (each step 360-degree/256).
  • High precision sprite zoom effect supports up to 256-step adjustment
  • Supports both alpha blending and additive blending
• Sound Process Unit (SPU)
  • 16 hardware PCM/ADPCM channels
  • Dynamic volume compressor
  • MP3 decoder
• Audio compressor engine which enhances audio quality
• JPEG CODEC
  • ISO/IEC 10918-1 baseline JPEG
  • High-speed decoding and encoding with resolution up to 64M pixels
  • Hardware Motion JPEG decoding and encoding (up to 1080p@30fps) for real-time video record and playback application
• Video-in & CMOS sensor interface and CCIR601/CCIR656 CSI standard supported.
• Two/one-lane MIPI CSI input supported
• Face Detection Engine for interactive application
• NAND FLASH controller with ECC and 4/8/12-bit BCH
• Eight-channel DMA controller with AES function
• Mono and 16 gray levels STN-LCD controller
• Rotating engine supports 90/180/270/360/Mirror/Flip function
• Y only rotating engine supports rotate at any angle
• Line-based rotating engine supports panels with different orient with frame buffer without extra bandwidth consumption.
• Two sets of TFT-LCD controller.
  • UPS051 (serial RGB)
  • UPS052 (serial RGB dummy)
  • Parallel RGB (6-6-6, 7-7-7, 8-8-8).
  • I80 (8-bit/16-bit/18-bit system bus) I/F type
  • CCIR601/CCIR656
  • Timing Controller for TFT-LCD drivers
  • Scaling engine inside with programmable up-scaling and down-scaling factor
  • Gamma Table Adjustment(TFT1 Only)
• Up to 4-lane MIPI DSI interface which supports panel resolution up to 1280x720 or 720x1280.
• Display adjustment engine which provides edge enhancement, R/G/B gamma table and auto hue adjustment
• Two sets of PSCAL supporting transform and zoom-in/out image data to the format supported by JPEG/ PPU/ DRAM
• One Y-only PSCAL for face-detection engine
• Image Processing Unit
  • width more than 2048 pixels
  • Address-remap supporting direct addressing and Coordinates addressing
  • Color-remap-only supporting ARGB155 and RGB565
  • Sixteen OP modes supported
  • Support Alpha transform
• Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB OHCI/EHCE host controller with built-in transceiver.
• Watchdog timer
• Real-time clock
• Eight 32-bit timers/counters with PWM output capability.
• Eight-channel quadrature decoder
• Two sets of SD 2.0/MMC interface
• Two sets of SPI (master/slave) interface with data rate up to 24Mbps.
• Three sets of UART (asynchronous serial I/O) or IrDA interface with baud rate up to 1.8432Mbps and 115.2Kbps; smart card interface (ISO7816) supported
• Three sets of I2C controller
• Four sets of I2S input with 24-bit resolution and up to 192KHz sample rate
• Four sets of I2S output with 24-bit resolution and up to 192KHz sample rate
• PDM to PCM converter which supports MEMS microphones with PDM interface
• Embedded Ethernet MAC hardware
• One set hardware SAD (Sum of Absolute Difference) engine
• 90 general programmable I/O ports (GPIO) with pull-high/low control
• Power management
• 2V DC2DC Feedback reference voltage out for core logic
• 3V to 2.8V~1.8V regulator for sensor’s power
• 3V to 2.5V~1.8V regulator for DDR memory
• Dedicated 3.3V to 3.0V LDO for audio ADC
• Dedicated 3.3V to 3.0V LDO for PLLs
• Low voltage reset
• RTC with independent power supply
• Power-down mode with low standby current, typically less than 10uA
• Two sets of programmable PLLs frequency from 144MHz to 1188MHz and 72MHz to 594MHz
• 16-bit stereo DAC (2-channel) for audio playback
• 16-bit ADC with MIC for audio recording
• 12-bit SAR ADC with 8 line-in channels and 800KMsps
• MIC with digital AGC (auto gain control)
• LFBGA108 package