产品资讯 - GPL98100UA

General Description

GPL98100UA, a highly integrated SoC (System-On a Chip) by Generalplus, is a good solution for multi-media applications.  It is developed with a high performance and power efficient ARM®'s ARM926EJ-S™ core operating at up to CPU/system 513/171MHz with significant enhancements in image processing, and power savings.  Other features include Chroma key engine, JPEG CODEC engine, TFT-LCD interface, Display adjustment engine, CMOS sensor interface, scaling engine, Picture Process Unit (PPU), 16-channel Sound Process Unit (SPU), audio compressor, USB 2.0 OHCI/EHCI, USB 2.0 HS device, etc. The GPL98100UA processor is designed to run programs directly on the SPI Flash via the SPI Flash controller, without external SDRAM, and the fastest SPI Flash clock can reach 85.5MHz (the system clock frequency is divided by 2).  For more information about its features, please refer to the following section.

Features

• ARM926EJ-S^™ CPU with both 16K-byte I/D-cache, embedded JTAG ICE, and working frequency up to 513MHz
• Memories
  • Internal SRAM memory
• In addition to the 64KB dedicated memory, internal memory can be shared from unused hardware memories. The shared memories can be set to consecutive addresses for ease of use. When all shareable memories are shared, the total internal memory size is 238KB for local data buffer and frame buffer.
• The powerful hardware performance should be used carefully with limited internal memory. Users need to consider the usage situation and calculate whether the internal memory is sufficient.
  • External SPI Flash memory via the SPI Flash controller
• The fastest clock output of the SPI Flash controller is 85.5MHz (System clock frequency divided by 2. The maximum operating frequency of SPI Flash highly depends on PCB load.)
• The SPI FLASH controller that allows CPU and other hardware IP to be linearly mapped and executed on external SPI Flash memory. In addition to 1-bit mode, 2-bit mode and 4-bit mode are also supported.
• Both graphics data(such as PPU Sprites/TEXTs data) and audio data(such as SPU tone/envelope data ) can be placed on the SPI Flash, and the hardware(PPU,SPU and so on) can access directly, just like the data is placed on the internal SRAM memory
  • External NAND Flash memory
• NAND FLASH controller with ECC and 4/8/12-bit BCH
• Due to the limited internal memory size, the use of NAND Flash should be carefully evaluated for feasibility.

• Chroma key engine with robust mechanism and low bandwidth requirement
• Picture Process Unit. (PPU)
  • 4 Text layers + 1024 internal Sprites + 4096 extended Sprites
  • QVGA/VGA output
  • Line-based operation
  • 320x240 LCD Resolution output
  • Texture mapping with anti-aliasing and bilinear interpolation
  • High precision sprite rotate effect supports up to 256-step (each step 360 degree/256).
  • High precision sprite zoom effect supports up to 256-step adjustment
  • Supports both alpha blending and additive blending
• Sound Process Unit (SPU)
  • 16 hardware PCM/ADPCM channels
  • Dynamic volume compressor
  • MP3 decoder
• Audio compressor engine which enhances audio quality
• JPEG CODEC
  • ISO/IEC 10918-1 baseline JPEG
  • High-speed decoding and encoding with resolution up to VGA
  • Due to the limited internal memory size, the use of JPEG CODEC should be carefully evaluated for feasibility.
• CMOS sensor interface and CCIR601/CCIR656 CSI standard supported.
  • Due to the limited internal memory size, the use of CMOS sensor should be carefully evaluated for feasibility.
• Eight-channel DMA controller with AES function
• Mono and 16 gray levels STN-LCD controller
• Y only rotating engine supports rotate at any angle
• Two TFT-LCD controllers
  • UPS051 (serial RGB)
  • UPS052 (serial RGB dummy)
  • Parallel RGB (6-6-6, 7-7-7, 8-8-8)
  • I80 (8-bit/16-bit/18-bit system bus) I/F type
  • CCIR601/CCIR656
  • Timing Controller for TFT-LCD drivers
  • Scaling engine inside with programmable up-scaling and down-scaling factor
  • Gamma Table Adjustment(TFT1 Only)
• Two sets of PSCAL supporting transform and zoom-in/out image data to the format supported by JPEG/ PPU
• One Y-only PSCAL
• Image Processing Unit
  • 640-pixel width
  • Address-remap supporting direct addressing and Coordinates addressing
  • Color-remap-only supporting ARGB155 and RGB565
  • Sixteen OP modes supported
  • Support Alpha transform
• Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB OHCI/EHCE host controller with built-in transceiver.
• Watchdog timer
• Real-time clock
• Eight 32-bit timers/counters with PWM output capability
• Eight-channel quadrature decoder
• Two sets of SD 2.0/MMC interface
• Two sets of SPI controller(master/slave)
  • Programmable master SCK clock frequency up to system clock divided by 2(85.5MHz, actual operating frequency depends on PCB loading and external SPI device.)
  • Support 1-bit/2-bit/4-bit IO mode
  • The SPI controller is used for general external peripheral control, and the CPU cannot directly execute the program through the SPI controller
• Three sets of UART (asynchronous serial I/O) or IrDA interface with baud rate up to 1.8432Mbps and 115.2Kbps; smart card interface (ISO7816) supported
• Three sets of I2C controller
• Four sets of I2S input with 24-bit resolution and up to 192KHz sample rate
• Four sets of I2S output with 24-bit resolution and up to 192KHz sample rate
• PDM to PCM converter which supports MEMS microphones with PDM interface
• One set hardware SAD (Sum of Absolute Difference) engine
• 90 general programmable I/O ports (GPIO) with pull-high/low control
• Power management
• 2V DC2DC Feedback reference voltage out for core logic
• 3V to 2.8V~1.8V regulator for sensor’s power
• Dedicated 3.3V to 3.0V LDO for audio ADC
• Dedicated 3.3V to 3.0V LDO for PLLs
• Low voltage reset
• RTC with independent power supply
• Power-down mode with low standby current, typically less than 10uA
• Programmable spread spectrum system PLL, frequency from 144MHz to 1026MH, for CPU, and with a divider, the frequency can also be provided to the system clock. If the spread spectrum function is enabled, it will be spreading down from the setting frequency by 5,000ppm. That is, the frequency of spread spectrum will be less than or equal to the setting frequency.  The spread spectrum function is disabled by default. 
• Programmable external PLL frequency from 72MHz to 594MHz.
• 16-bit stereo DAC (2-channel) for audio playback
• 16-bit ADC with MIC for audio recording
• 12-bit SAR ADC with 8 line-in channels and 800Ksps
• MIC with digital AGC (auto gain control)
• LQFP128 package