产品资讯 - GPM4730A

General Description

GPM4730A, a highly integrated SoC (System-On a Chip) by Generalplus, is a high cost-performance ratio solution for multi-media and video streaming applications.  It is developed with a high performance and power efficient ARM’s Cortex M4F core operating at up to 193.5MHz with significant enhancements in image, video processing, and power savings.  Other features include DDR memory, 720p30 H.264/JPEG CODEC engine, HD 720p HDMI interface, TFT-LCD interface, CMOS sensor interface, MIPI CSI interface, scaling engine, Picture Process Unit (PPU), 16-channel Sound Process Unit (SPU), USB 2.0 OHCI/EHCI, USB 2.0 HS device, etc. GPM4730A processor is designed to connect with various types of memory card interfaces such as SD and MMC.  For more information about its features, please refer to the following section.

Features

• ARM’s Cortex M4F CPU with 8K-byte unified ID-cache, floating point co-processor, write buffer, embedded JTAG/SWD ICE, and working frequency up to 193.5MHz.
• 128KB SRAM for local data buffer.
• Embedded 256Mb DDR SDRAM.
• SPI FLASH controller, allowing CPU directly runs program on it. Supports 1-bit/2-bit/4-bit IO mode.
• Picture Process Unit. (PPU)
  • Four Text layers + 1024 internal Sprites + 4096 extended Sprites.
  • Virtual 3D effect for text and sprite.
  • QVGA/VGA/D1 and arbitrary size up to 2032x2032 output.
  • Line-based or frame-based operation.
  • 1024x768 LCD Resolution output.
  • Texture mapping with anti-aliasing and bilinear interpolation.
• Sound Process Unit. (SPU)
  • 16 hardware PCM/ADPCM channels.
  • Built-in dynamic volume compressor.
• JPEG CODEC.
  • ISO/IEC 10918-1 baseline JPEG.
  • High-speed decoding and encoding with resolution up to 64MPixel.
  • Hardware Motion JPEG decoding and encoding (up to 720p@30fps) for real-time video record and playback application.
• 264 CODEC
  • 264 baseline profile CODEC
  • Up to 720p30 for real-time video record and playback application
• Video-in & CMOS sensor interface and CCIR601/CCIR656 CSI standard supported.
• One set of two-lane or two sets of one-lane MIPI CSI input supported
• Face Detection Engine for interactive application.
• NAND FLASH controller with ECC and 4/8/12-bit BCH
• 1/2/4-bit SPI FLASH controller, capable of running program on SPI directly.
• Eight-channel DMA controller with AES/DES/3DES function.
• 720p HDMI output with VGA to 720p up-scaling engine.
• Mono and 16 gray levels STN-LCD controller
• Rotating engine supports 90/180/270/360/Mirror/Flip function
• TFT-LCD controller.
  • UPS051 (serial RGB)
  • UPS052 (serial RGB dummy)
  • Parallel RGB (6-6-6, 7-7-7, 8-8-8)
  • I80 (8-bit/16-bit/18-bit system bus) I/F type
  • CCIR601/CCIR656
  • Built-in Timing Controller for TFT-LCD drivers.
  • Scaling engine inside with programmable up-scaling and down-scaling factor.
• Embedded ISP (Image Processing Unit), supports raw data sensor up to 5M pixels
  • Histogram statistics for auto brightness and contrast.
  • Programmable RGB gamma correction.
  • Color conversion matrix for various post-image processing.
  • WDR
  • Sharpen
  • De-noise
  • Bad-pixel cancelation
• Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB OHCI/EHCE host controller with built-in transceiver.
• Watchdog timer
• Real-time clock
• Eight 32-bit timers/counters with PWM output capability.
• Eight-channel quadrature decoder
• Two sets of SD 2.0/MMC interface
• Two sets of SPI (master/slave) interface with data rate up to 24Mbps
• Three sets of UART (asynchronous serial I/O) or IrDA interface with baud rate up to 1.8432Mbps and 115.2Kbps. Smart card interface (ISO7816) is also supported.
• Three sets of I2C controller
• CEC controller
• Four sets of I2S input with 24-bit resolution and up to 192KHz sample rate
• Four sets of I2S output with 24-bit resolution and up to 192KHz sample rate
• 72 general programmable I/O ports (GPIO) with pull-high/low control
• Power management
• Built-in 3.3V to 1.2V regulator for core logic
• Built-in 3.3V to 2.8V regulator for sensor’s power
• Built-in 3.3V to 2.5V regulator for DDR memory
• Low voltage reset
• RTC with independent power supply
• Fast boot from power-down mode with boot time less than 1ms
• Power-down mode with low standby current, typically less than 20uA
• Programmable PLL frequency from 12MHz to 193.5MHz
• 16-bit stereo DAC (2-channel) for audio playback
• 16-bit stereo ADC with MIC and LINEINR/LINEINL for audio recording
• 12-bit SAR ADC with 3 line-in channels and 100Ksps
• MIC with digital AGC (auto gain control)
• LQFP128 package