GPM8F3496A is a highly integrated microcontroller which integrates a pipelined 1T 8051 CPU, 12K byte external data memory(XRAM), 256-byte internal data memory(IDM) and 96K-byte program memory. It supports up to 56 programmable multi-functional I/Os, Timer0/1, CCP0/1/2, UART0/1, two sets of SPI (master/slaver), two sets of I2C (master/slaver), one 8-bit current DAC, two sets of analog comparator, one set real time counter, one set of 64MHz PLL, 16-bit X 16-bit multiplier, 32-bit / 16-bit divider, 16-bit adder, 16-bit subtractor, 32-bit shifter, one set of 24 extend and two internal input channels SAR ADC with 12-bit resolution and full speed USB function for general-purpose application. It operates with a wide range of working voltage that from 2.2V to 5.5V. For power saving, GPM8F3496A provides a power management unit to manage the system power. Moreover, there is one on-chip debug circuit with two pins to facilitate full speed in-system debug.
Features
CPU
High speed, high performance 1T 8051
100% software compatible with industry standard 8051
Pipeline RISC architecture enables to execute instructions 10 times faster than standard 8051
Up to 64MHz clock operation
Memories
12K bytes XRAM
256 bytes internal Data Memory (IDM) SRAM
96K bytes FLASH with high endurance
Minimum 20K program/erase cycles
Minimum 30us program time
Minimum 30ms erase time
Minimum 100 years data retention
1KB page size
Flexible memory size for AP and ISP
Memory protection mechanism for FLASH access
Programmable read-only level for software security
Clock Management
Internal oscillator with 8MHz±2% @ 2V~5.5V
Internal oscillator with PLL : 64MHz @2.2~5.5V
Internal oscillator with 32KHz ± 50% @2.2~5.5V
Crystal input with 8MHz
Crystal input with 32KHz
Power Management
One Sleep mode for power saving
Interrupt Management
22 interrupt sources
6 wakeup sources
Up to 7 external interrupt sources
Up to 16 keyboard interrupt sources
Reset Management
Power On Reset (POR)
Low Voltage Reset (LVR)
Pad Reset (PAD_RST)
Watchdog Reset (WDT_RST)
Software Reset (S/W_RST)
FLASH Access Error Reset (ADDR_ERR_RST)
Programmable Watchdog Timer
A time-base generator
An event timer
System supervisor
I/O Ports
56 multifunction bi-direction I/Os
Each incorporated with pull-up resistor, pull-down resistor, output high, output low , output driving capability and floating input which depending on programmer’s settings on the corresponding registers
I/O ports with 5mA current sink @VDD=3.3V
I/O ports with 6mA current drive@VDD=3.3V
Two 16-bit Timer/Counter (Timer0/1)
Timer mode with five source selectable
13-bit/ 16-bit up-count timers
Auto reload 8-bit timers
Two 8-bit timers
Externally gated event counters
UART0/1
One synchronous mode
Three asynchronous modes
SPI0 /1 (master / slaver mode)
Programmable phase and polarity of master clock
Programmable master SPI clock frequency
Max SPI clock: 32MHz (Fpll /2) @64MHz
Programmable data transfer with CPU mode or DMA mode
A/D Converter
24 extend and 2 internal input channels 12-bit resolution ADC
conversion rate@ 880Ksps
Control independent per set
Programmable data transfer with CPU mode or DMA mode
Programmable A/D conversion data width
Support 8 sets ADC_VREF voltage select
I2C0/1 (master / slaver mode)
Programmable master I2C clock frequency
Max I2C clock:500KHz (Fpll /128) @64MHz
MDU
16-bit X 16-bit signed multiplier
32-bit / 16-bit signed divider
16-bit + 16-bit signed adder
16-bit - 16-bit signed subtractor
32-bit arithmetic shifter.
Key Change
Programmable 16 IOs key change interrupt
Analog Comparator
Two analog comparators
32-stage selectable reference voltage
DMA
One channel DMA supported
DMA path SPI RX to XRAM / SPI TX to XRAM / ADC to XRAM / XRAM to XRAM
Current DAC
Supporting 8 bit current DAC
4K~16KHz sampling frequency
Up to 4.5mA full scale output current with VDD= 5V
RTC
Programmable real-time-counter wakeup source. 1 Hour/ 30mimute/ 60 second/ 1 second / halt second
Three Powerful CCP 0/1/2 unit with 16-bit resolution (Compare / Capture / PWM Unit)