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GPLB301A(OTP)*

Description
Document
Tools
Sample Code
Video

Working Voltage (V)	Max. CPU Speed (MHz)	ROM (Byte)	RAM (Byte)	I/O	COMxSEG Option	Bias	Duty	Audio Output	32K OSC.	Serial I/F	Bus I/F	SPI/UART	WDT	LVD/LVR
2.4~5.5	10	512K	4288	30	32X74	1/3, 1/4, 1/5, 1/6	1/4, 1/8, 1/16, 1/32	PWM/DAC	ROSC/X'TAL	√	√	-/√	√	√/√

General Description

The GPLB301A, an 8-bit CMOS microprocessor, contains 4288 bytes working RAM, 512K bytes OTP memory, 30 I/Os, interrupt/wakeup controller, UART for serial communication, Serial SRAM interface and Bus memory interface for memory expansion, and automatic display controller/driver for LCD. It is an OTP (one-time-programming) version for GPLB30/ GPLB32 /GPLB33 /GPLB37 /GPLB38B. The embedded OTP memory enables users to customize application programs fast and conveniently. Users may use GPLB301A for prototyping and then use GPLB30/ GPLB32/ GPLB33/ GPLB37/ GPLB38B for mass production. The pin sequence of GPLB301A is compatible with GPLB32 and GPLB37. It also features one PWM driver with two audio channels to produce attractive sound effects easily. Its large OTP area can be used to store both program and audio data (speech duration approx. 138 seconds at 7KHz sampling rate using a 4-bit ADPCM). The built-in UART speeds up data transmission between two devices. Furthermore, a SLEEP (power-down) function is also built in to extend power life. The GPLB301A is designed with state-of-the-art technology to fulfill LCD application needs, especially for hand-held products.

Features

GPLB301 can emulate varieties of GPLB3x series, The GPLB301 is able to emulate the following series via options.

Body selected	ALL	GPLB30A	GPLB32A	GPLB33A	GPLB33B	GPLB37A	GPLB38B
RAM Size	4288 Bytes	2752 Bytes	1215 Bytes	1216 Bytes	1024 Bytes	1216 Bytes	1216 Bytes
OTP Size	512K Bytes	96K Bytes	512K Bytes	64K Bytes	96K Bytes	256K Bytes	512K Bytes
Wake-up Sources	6	6	6	6	5	6	5
Interrupt Sources	7	7	7	7	5	7	5
UART	Yes	Yes	Yes	Yes	-	Yes	-
Serial SRAM Interface	Yes	Yes	Yes	Yes	-	Yes	-
BUS Memory Interface	Yes	Yes	-	-	-	-	-
Voltage Regulator for External Memory Devices	Yes	Yes	-	-	-	-	-
Segment	74	70	74	52	78	74	64
Common	32	16	32	16	16	32	16
LCD Dots	2368	1120	2368	832	768	2368	1024
Bias	1/5, 1/6	1/5	1/5, 1/6	1/5	1/3, 1/4, 1/5	1/5, 1/6	185
Duty	1/16, 1/32	1/16	1/16, 1/32	1/16	1/4, 1/8, 1/16	1/16,1/32	1/16
LCD RAM	296 Bytes	140 Bytes	296 Bytes	104 Bytes	96 Bytes	296 Bytes	128 Bytes
Max. I/O Pins	30	29	28	24	24	28	12
PA	[7:0]	[7:0]	[7:0]	[7:0]	[7:0]	[7:0]	[7:0]
PB	[7:0]	[7:0]	[5:0]	[7:0]	[7:0]	[5:0]	-
PC	[7:0]	[7:0]	[7:0]	[7:0]	[7:0]	[7:0]	[7:4]
PD	[5:0]	[4:0]	[5:0]	-	-	[5:0]	-
Dedicated I/Os	PA[0:7], PB[0:7], PC[0:7]	PA[0:4]	PA[0:5]	PA[0:6]	PA[0:7], PC[0:1]	PA[0:5]	PA[0:7], PC[7:4]
Shared Pin I/Os: PA	-	PA[5:7] / SEG[69:67]	PA[6:7] / SEG[63:62]	PA[7] / SEG[51]	PB[0:7] / SEG[41:34]	PA[6:7] / SEG[63:62]	-
Shared Pin I/Os: PB	-	PB[0:7] / BMI AD BUS[0:7] / SEG[64:57]	PB[0:5] / SEG[69:64] / COM[21:16]	PB[0:7] / SEG[46:39]	PC[2:7] / SEG[47:42]	PB[0:5] / SEG[69:64] / COM[21:16]	-
Shared Pin I/Os: PC[0:1]	-	PC[0:1] / BMI MC[0:1] / SSRAM SDA, SCK	PC[0:1] / SSRAM SCK, SDA / SEG [61:60]	PC[0:1] / SSRAM SCK, SDA	-	PC[0:1] / SSRAM SCK, SDA / SEG[61:60]	-
Shared Pin I/Os: PC[2:3]	-	PC[2:3] / UART Tx / Rx / SEG[66:65]	PC[2:3] / UART Tx / Rx	PC[2:3] / UART Tx / Rx	-	PC[2:3] / UART Tx / Rx
Shared Pin I/Os: PC[4:5]	-	PC[4:5] / SEG[56:55] / Ext_I, Ext_CK	PC[4:5] / SEG[73:72] / COM[25:24] / Ext_I, Ext_CK	PC[4:5] / SEG[50:49] / Ext_I, Ext_CK	-	PC[4:5] / SEG[73:72] / COM[25:24] / Ext_I, Ext_CK	-
Shared Pin I/Os: PC[6:7]	-	PC[6:7] / SEG[54:53]	PC[6:7] / SEG[71:70] / COM[23:22]	PC[6:7] / SEG[48:47]	-	PC[6:7] / SEG[71:70] / COM[23:22]	-
Shared Pin I/Os: PD	PD[0:5] / COM[31:26]	PD[0:4] / SEG[52:48]	PD[0:5] / COM[31:26]	-	-	PD[0:5] / COM[31:26]	-