GPCD3T080B 
| Type | ROM | I/O | PWM I/O | SPU | SPI | QD | Touch | CMPIO | IRQ | NMI |
|---|---|---|---|---|---|---|---|---|---|---|
| Real Chip | 256K (MASK) | 24 Port A/B/D | 12 | 1-CH | V | V | V | V | 20 | 7 |
General Description
GPCD3T080B features a maximum of 2M-byte factory programmed OTP memory, up to 1024-byte working SRAM, three 12-bit timers, 16~32 general I/Os, two 12-bit current DAC and one 14-bit audio PWM driver. The microprocessor can implement software based on audio processing, function control and others. For audio processing, melody and speech can be mixed into one output. GPCD3T080A is implemented with a high performance SPU voice engine for playing one to eight channels of high-quality sound voice in ADPCM/PCM data format. It operates in a wide voltage range, from 2.2V through 5.5V, along with low voltage reset function. In addition, a sleep mode is designed to save powers for those applications with limited power resources available. A Serial Peripheral Interface (SPI) controller is also equipped to facilitate communication function with other devices and components.
Features
- 8-bit micro-processor
- Max. 1024-byte SRAM
- Operating voltage: 2.2V – 5.5V
- Max. CPU operating speed: 8.0MHz (Fosc:16MHz)
- Five wakeup sources
- 20 IRQs & 7 NMI Interrupts
- Internal built-in regulator to supply core power
- SPU(Sound Processing Unit) engine
- Supports 4-bit ADPCM data format and TAG mode
- Supports special tag, such as Silence Tag and Event tag
- 8-voice polyphony
- Two software channels with noise filter function to playback high quality voice
- Low Voltage Detection
- 8-level (2.2V/ 2.4V/ 2.6V/ 2.8V/ 3.0V/ 3.2V/ 3.4/ 3.6V) voltage detector
- Low Voltage Reset
- Peripherals
- Max. 32 I/O pins (IOA[7:0], IOB[7:0], IOC[7:0], IOD[7:0]) (varied by IC)
- 8~12 I/Os with high sink current (varied by IC)
- Key wakeup/interrupt function
- Built-in 32.768KHz oscillator circuit for real time clock function (X’tal or R-osc)
- Built-in R-oscillator (external resistor is needed), X’tal or internal R-oscillator (only 16MHz available for IOSC) for system operating clock
- Internal time base generator
- Three 12-bit timers/counters; TMA with capture and comparison function, TMB/TMC with comparison function (Programmable and auto reload)
- Watchdog function
- 14-bit PWM driver for driving speaker directly
- Two 12-bit current DACs
- IR output
- Max. 12 hardware PWMIOs
- One SPI serial interface I/Os
- Hardware Touch function
- One comparator with PGA
- 8-channel of SPU engine with ADPCM/PCM wave table
- Sleep mode to reduce power consumption
Confirmation Sheet
GPCD3T_6T_9T SeriesV18_cm(epdf).pdf
Data Sheet
GPCDXTXXXBV14_ds.pdf
Application / Engineering Note
AN0203-GPCDxT_LowVoltageResetFailIssue-16.pdf
Sample Codes :
GPCD2T Module Code - V1.0.1
